1. Field of the Invention
This invention relates to an incrementer to be incorporated in a microcomputer system or the like for use as, for example, a program counter.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing the arrangement of a conventional n-bit incrementer.
In the diagram, reference numerals 1 and 2 designate signal lines for non-overlapping clocks .phi., .phi., and reference numerals 3, 3 . . . designate bit cells constituting the incrementer. As shown, the n-bit incrementer is comprised of n-bit cells 3.
In each bit cell 3, reference numeral 4 is a carry input terminal to which a carry from a next lower-order bit cell is inputted, numeral 5 is a carry output terminal for outputting a carry to a next higher-order bit cell, and reference numeral 6 is an output terminal for outputting a value resulting from an increment. Reference numeral 7 is a latch circuit which retains the incremented value. Reference numeral 8 is an increment operation circuit which, when a carry from the carry input terminal 4 is inputted thereto, adds "1" to the value retained in the latch circuit 7, and which outputs the result of the addition to the latch circuit 7 and a carry resulting from the addition to the carry output terminal 5.
Reference characters O.sub.0, O.sub.1, . . . O.sub.i ; . . . O.sub.n -1 designate output signals for incremented values in each bit cell. Carry inputs to the bit cell of the 0th bit order are constantly set at "1" so that an increment is carried out each time the clock .phi. becomes "1".
Next the manner of operation of the above described conventional incrementer is explained. In each bit cell 3, the increment operation circuit 8, as FIG. 1 illustrates, carries out addition of a carry from the carry input terminal 4 to the data retained in the latch circuit 7. A sum resulting from the addition is outputted as a value of increment to the latch circuit 7 and a carry is outputted from the carry output terminal 5.
The input/output relations in this connection are tabulated in FIG. 2. If either one of the inputs is "1" in value and the other is "0", value "1" is outputted as a value of increment, while otherwise value "0" is outputted as such. At the carry outputs, value "1" appears only when both inputs are "1" in value. Referring to the timing of operation of each bit cell 3, when .phi.="1", data is inputted to the increment operation circuit 8 for operation therein, and the results of the operation a carry is outputted while .phi.="1" so that the output is inputted as an input data to a next higher-order increment operation circuit. Thus, new values are sequentially established from lower digit orders to higher digit orders. Output of a sum resulting from an addition is outputted from the terminal 6 at the timing of clock .phi.="1", and the sum is held as such in the latch circuit 7.
Timings for operation of the entire incrementer are shown in a timing chart of FIG. 3.
Carry inputs to the bit cell in the 0th bit order are constantly set to "1". Therefore, value "1" is added to the bit cell in the 0th bit order each time .phi.="1" is reached, and such sum and such carry as obtained from the addition are outputted accordingly. This carry is inputted as a carry input to the increment operation circuit in the first bit order, and it is added to the data in the latch circuit in the same way. Thus, a sum and a carry are calculated, and the carry is inputted as a carry input to the increment operation circuit 8 in a next higher bit order.
An incremented value is established only when a carry is propagated to the nth bit order after n-1 series of such carry propagation, and at succeeding series of timings for .phi.="1", incremented values O.sub.0, O.sub.1, . . . O.sub.i ; . . . O.sub.n-1 are sequentially output as such. A carry takes the process of propagating through n-1 units of inverters and NAND gates, and a delay is caused accordingly. This delay is generally called "carry propagation delay".
With such conventional incrementer as above described, decoding is required for selection of a word line, when an incremented binary digit indicates an address in a memory or the like. Therefore, a delay due to such decoding is inevitable. Another difficulty with the conventional incrementer is that increment operation of a bit cell at a higher bit order is influenced by the carry output of a bit cell at a lower bit order, which is a cause of a carry propagation delay.